462 lines
No EOL
12 KiB
C
462 lines
No EOL
12 KiB
C
#if defined(CPU_X86) && (defined(COMPILER_MSVC) || defined(COMPILER_GCC))
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#define X86ASM
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/* gcc 2.95 royally screws up stack alignments on variables */
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#if ((defined(COMPILER_MSVC) && (COMPILER_MSVC >= COMPILER_MSVC_VS6PP)) || (defined(COMPILER_GCC) && (COMPILER_GCC >= 30000)))
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#define X86ASM_SSE
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#define X86ASM_SSE2
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#endif
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#if ((defined(COMPILER_MSVC) && (COMPILER_MSVC >= COMPILER_MSVC_VS2005)) || (defined(COMPILER_GCC) && (COMPILER_GCC >= 40102)))
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#define X86ASM_SSSE3
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#endif
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#if ((defined(COMPILER_MSVC) && (COMPILER_MSVC >= COMPILER_MSVC_VS2010SP1)) || (defined(COMPILER_GCC) && (COMPILER_GCC >= 40400)))
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#define X86ASM_AVX
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#define X86ASM_XOP
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#endif
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#if ((defined(COMPILER_MSVC) && (COMPILER_MSVC >= COMPILER_MSVC_VS2012)) || (defined(COMPILER_GCC) && (COMPILER_GCC >= 40700)))
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#define X86ASM_AVX2
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#endif
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#endif
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#if defined(CPU_X86_64) && defined(COMPILER_GCC)
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#define X86_64ASM
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#define X86_64ASM_SSE2
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#if (COMPILER_GCC >= 40102)
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#define X86_64ASM_SSSE3
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#endif
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#if (COMPILER_GCC >= 40400)
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#define X86_64ASM_AVX
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#define X86_64ASM_XOP
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#endif
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#if (COMPILER_GCC >= 40700)
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#define X86_64ASM_AVX2
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#endif
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#endif
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#if defined(COMPILER_MSVC) && (defined(CPU_X86_FORCE_INTRINSICS) || defined(CPU_X86_64))
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#define X86_INTRINSIC
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#if defined(CPU_X86_64) || defined(X86ASM_SSE)
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#define X86_INTRINSIC_SSE
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#endif
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#if defined(CPU_X86_64) || defined(X86ASM_SSE2)
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#define X86_INTRINSIC_SSE2
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#endif
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#if (COMPILER_MSVC >= COMPILER_MSVC_VS2005)
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#define X86_INTRINSIC_SSSE3
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#endif
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#if (COMPILER_MSVC >= COMPILER_MSVC_VS2010SP1)
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#define X86_INTRINSIC_AVX
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#define X86_INTRINSIC_XOP
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#endif
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#if (COMPILER_MSVC >= COMPILER_MSVC_VS2012)
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#define X86_INTRINSIC_AVX2
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#endif
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#endif
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#if defined(COMPILER_GCC) && defined(CPU_X86_FORCE_INTRINSICS)
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#define X86_INTRINSIC
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#if defined(__SSE__)
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#define X86_INTRINSIC_SSE
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#endif
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#if defined(__SSE2__)
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#define X86_INTRINSIC_SSE2
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#endif
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#if defined(__SSSE3__)
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#define X86_INTRINSIC_SSSE3
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#endif
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#if defined(__AVX__)
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#define X86_INTRINSIC_AVX
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#endif
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#if defined(__XOP__)
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#define X86_INTRINSIC_XOP
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#endif
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#if defined(__AVX2__)
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#define X86_INTRINSIC_AVX2
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#endif
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#endif
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/* only use simd on windows (or SSE2 on gcc)! */
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#if defined(CPU_X86_FORCE_INTRINSICS) || defined(X86_INTRINSIC)
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#if defined(X86_INTRINSIC_SSE)
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#include <mmintrin.h>
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#include <xmmintrin.h>
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typedef __m64 qmm;
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typedef __m128 xmm;
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typedef __m128d xmmd;
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#endif
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#if defined(X86_INTRINSIC_SSE2)
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#include <emmintrin.h>
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typedef __m128i xmmi;
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#endif
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#if defined(X86_INTRINSIC_SSSE3)
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#include <tmmintrin.h>
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#endif
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#if defined(X86_INTRINSIC_AVX)
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#include <immintrin.h>
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#endif
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#if defined(X86_INTRINSIC_XOP)
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#if defined(COMPILER_MSVC)
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#include <intrin.h>
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#else
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#include <x86intrin.h>
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#endif
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#endif
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#if defined(X86_INTRINSIC_AVX2)
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typedef __m256i ymmi;
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#endif
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#endif
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#if defined(X86_INTRINSIC_SSE2)
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typedef union packedelem8_t {
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uint8_t u[16];
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xmmi v;
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} packedelem8;
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typedef union packedelem32_t {
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uint32_t u[4];
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xmmi v;
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} packedelem32;
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typedef union packedelem64_t {
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uint64_t u[2];
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xmmi v;
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} packedelem64;
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#else
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typedef union packedelem8_t {
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uint8_t u[16];
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uint32_t dw[4];
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} packedelem8;
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typedef union packedelem32_t {
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uint32_t u[4];
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uint8_t b[16];
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} packedelem32;
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typedef union packedelem64_t {
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uint64_t u[2];
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uint8_t b[16];
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} packedelem64;
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#endif
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#if defined(X86_INTRINSIC_SSSE3)
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static const packedelem8 ALIGN(16) ssse3_rotl16_32bit = {{2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13}};
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static const packedelem8 ALIGN(16) ssse3_rotl8_32bit = {{3,0,1,2,7,4,5,6,11,8,9,10,15,12,13,14}};
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#endif
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/*
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x86 inline asm for gcc/msvc. usage:
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asm_naked_fn_proto(return_type, name) (type parm1, type parm2..)
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asm_naked_fn(name)
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a1(..)
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a2(.., ..)
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a3(.., .., ..)
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64bit OR 0 paramters: a1(ret)
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32bit AND n parameters: aret(4n), eg aret(16) for 4 parameters
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asm_naked_fn_end(name)
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*/
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#if defined(X86ASM) || defined(X86_64ASM)
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#if defined(COMPILER_MSVC)
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#pragma warning(disable : 4731) /* frame pointer modified by inline assembly */
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#define a1(x) __asm {x}
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#define a2(x, y) __asm {x, y}
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#define a3(x, y, z) __asm {x, y, z}
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#define a4(x, y, z, w) __asm {x, y, z, w}
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#define aj(x) __asm {x}
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#define asm_align8 a1(ALIGN 8)
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#define asm_align16 a1(ALIGN 16)
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#define asm_calling_convention STDCALL
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#define aret(n) a1(ret n)
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#define asm_naked_fn_proto(type, fn) static NAKED type asm_calling_convention fn
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#define asm_naked_fn(fn) {
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#define asm_naked_fn_end(fn) }
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#elif defined(COMPILER_GCC)
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#define GNU_AS1(x) #x ";\n"
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#define GNU_AS2(x, y) #x ", " #y ";\n"
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#define GNU_AS3(x, y, z) #x ", " #y ", " #z ";\n"
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#define GNU_AS4(x, y, z, w) #x ", " #y ", " #z ", " #w ";\n"
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#define GNU_ASFN(x) "\n_" #x ":\n" #x ":\n"
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#define GNU_ASJ(x) ".att_syntax prefix\n" #x "\n.intel_syntax noprefix\n"
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#define a1(x) GNU_AS1(x)
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#define a2(x, y) GNU_AS2(x, y)
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#define a3(x, y, z) GNU_AS3(x, y, z)
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#define a4(x, y, z, w) GNU_AS4(x, y, z, w)
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#define aj(x) GNU_ASJ(x)
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#define asm_align8 ".p2align 3,,7"
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#define asm_align16 ".p2align 4,,15"
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#if defined(OS_WINDOWS)
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#define asm_calling_convention CDECL
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#define aret(n) a1(ret)
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#if defined(X86_64ASM)
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#define asm_naked_fn(fn) ; __asm__ ( \
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".text\n" \
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asm_align16 GNU_ASFN(fn) \
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"subq $136, %rsp;" \
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"movdqa %xmm6, 0(%rsp);" \
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"movdqa %xmm7, 16(%rsp);" \
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"movdqa %xmm8, 32(%rsp);" \
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"movdqa %xmm9, 48(%rsp);" \
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"movdqa %xmm10, 64(%rsp);" \
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"movdqa %xmm11, 80(%rsp);" \
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"movdqa %xmm12, 96(%rsp);" \
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"movq %rdi, 112(%rsp);" \
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"movq %rsi, 120(%rsp);" \
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"movq %rcx, %rdi;" \
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"movq %rdx, %rsi;" \
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"movq %r8, %rdx;" \
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"movq %r9, %rcx;" \
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"call 1f;" \
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"movdqa 0(%rsp), %xmm6;" \
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"movdqa 16(%rsp), %xmm7;" \
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"movdqa 32(%rsp), %xmm8;" \
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"movdqa 48(%rsp), %xmm9;" \
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"movdqa 64(%rsp), %xmm10;" \
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"movdqa 80(%rsp), %xmm11;" \
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"movdqa 96(%rsp), %xmm12;" \
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"movq 112(%rsp), %rdi;" \
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"movq 120(%rsp), %rsi;" \
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"addq $136, %rsp;" \
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"ret;" \
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".intel_syntax noprefix;" \
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".p2align 4,,15;" \
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"1:;"
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#else
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#define asm_naked_fn(fn) ; __asm__ (".intel_syntax noprefix;\n.text\n" asm_align16 GNU_ASFN(fn)
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#endif
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#else
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#define asm_calling_convention STDCALL
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#define aret(n) a1(ret n)
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#define asm_naked_fn(fn) ; __asm__ (".intel_syntax noprefix;\n.text\n" asm_align16 GNU_ASFN(fn)
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#endif
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#define asm_naked_fn_proto(type, fn) extern type asm_calling_convention fn
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#define asm_naked_fn_end(fn) ".att_syntax prefix;\n" );
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#define asm_gcc() __asm__ __volatile__(".intel_syntax noprefix;\n"
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#define asm_gcc_parms() ".att_syntax prefix;"
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#define asm_gcc_trashed() __asm__ __volatile__("" :::
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#define asm_gcc_end() );
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#else
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need x86 asm
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#endif
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#endif /* X86ASM || X86_64ASM */
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#if defined(CPU_X86) || defined(CPU_X86_64)
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typedef enum cpu_flags_x86_t {
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cpu_mmx = 1 << 0,
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cpu_sse = 1 << 1,
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cpu_sse2 = 1 << 2,
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cpu_sse3 = 1 << 3,
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cpu_ssse3 = 1 << 4,
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cpu_sse4_1 = 1 << 5,
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cpu_sse4_2 = 1 << 6,
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cpu_avx = 1 << 7,
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cpu_xop = 1 << 8,
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cpu_avx2 = 1 << 9
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} cpu_flags_x86;
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typedef enum cpu_vendors_x86_t {
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cpu_nobody,
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cpu_intel,
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cpu_amd
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} cpu_vendors_x86;
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typedef struct x86_regs_t {
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uint32_t eax, ebx, ecx, edx;
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} x86_regs;
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#if defined(X86ASM)
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asm_naked_fn_proto(int, has_cpuid)(void)
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asm_naked_fn(has_cpuid)
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a1(pushfd)
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a1(pop eax)
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a2(mov ecx, eax)
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a2(xor eax, 0x200000)
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a1(push eax)
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a1(popfd)
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a1(pushfd)
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a1(pop eax)
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a2(xor eax, ecx)
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a2(shr eax, 21)
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a2(and eax, 1)
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a1(push ecx)
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a1(popfd)
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a1(ret)
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asm_naked_fn_end(has_cpuid)
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#endif /* X86ASM */
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static void NOINLINE
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get_cpuid(x86_regs *regs, uint32_t flags) {
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#if defined(COMPILER_MSVC)
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__cpuid((int *)regs, (int)flags);
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#else
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#if defined(CPU_X86_64)
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#define cpuid_bx rbx
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#else
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#define cpuid_bx ebx
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#endif
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asm_gcc()
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a1(push cpuid_bx)
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a2(xor ecx, ecx)
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a1(cpuid)
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a2(mov [%1 + 0], eax)
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a2(mov [%1 + 4], ebx)
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a2(mov [%1 + 8], ecx)
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a2(mov [%1 + 12], edx)
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a1(pop cpuid_bx)
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asm_gcc_parms() : "+a"(flags) : "S"(regs) : "%ecx", "%edx", "cc"
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asm_gcc_end()
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#endif
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}
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#if defined(X86ASM_AVX) || defined(X86_64ASM_AVX)
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static uint64_t NOINLINE
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get_xgetbv(uint32_t flags) {
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#if defined(COMPILER_MSVC)
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return _xgetbv(flags);
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#else
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uint32_t lo, hi;
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asm_gcc()
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a1(xgetbv)
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asm_gcc_parms() : "+c"(flags), "=a" (lo), "=d" (hi)
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asm_gcc_end()
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return ((uint64_t)lo | ((uint64_t)hi << 32));
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#endif
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}
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#endif // AVX support
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#if defined(SCRYPT_TEST_SPEED)
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size_t cpu_detect_mask = (size_t)-1;
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#endif
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static size_t
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detect_cpu(void) {
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union { uint8_t s[12]; uint32_t i[3]; } vendor_string;
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cpu_vendors_x86 vendor = cpu_nobody;
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x86_regs regs;
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uint32_t max_level, max_ext_level;
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size_t cpu_flags = 0;
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#if defined(X86ASM_AVX) || defined(X86_64ASM_AVX)
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uint64_t xgetbv_flags;
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#endif
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#if defined(CPU_X86)
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if (!has_cpuid())
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return cpu_flags;
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#endif
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get_cpuid(®s, 0);
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max_level = regs.eax;
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vendor_string.i[0] = regs.ebx;
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vendor_string.i[1] = regs.edx;
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vendor_string.i[2] = regs.ecx;
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if (scrypt_verify(vendor_string.s, (const uint8_t *)"GenuineIntel", 12))
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vendor = cpu_intel;
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else if (scrypt_verify(vendor_string.s, (const uint8_t *)"AuthenticAMD", 12))
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vendor = cpu_amd;
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if (max_level & 0x00000500) {
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/* "Intel P5 pre-B0" */
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cpu_flags |= cpu_mmx;
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return cpu_flags;
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}
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if (max_level < 1)
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return cpu_flags;
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get_cpuid(®s, 1);
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#if defined(X86ASM_AVX) || defined(X86_64ASM_AVX)
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/* xsave/xrestore */
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if (regs.ecx & (1 << 27)) {
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xgetbv_flags = get_xgetbv(0);
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if ((regs.ecx & (1 << 28)) && (xgetbv_flags & 0x6)) cpu_flags |= cpu_avx;
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}
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#endif
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if (regs.ecx & (1 << 20)) cpu_flags |= cpu_sse4_2;
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if (regs.ecx & (1 << 19)) cpu_flags |= cpu_sse4_2;
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if (regs.ecx & (1 << 9)) cpu_flags |= cpu_ssse3;
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if (regs.ecx & (1 )) cpu_flags |= cpu_sse3;
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if (regs.edx & (1 << 26)) cpu_flags |= cpu_sse2;
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if (regs.edx & (1 << 25)) cpu_flags |= cpu_sse;
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if (regs.edx & (1 << 23)) cpu_flags |= cpu_mmx;
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if (cpu_flags & cpu_avx) {
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if (max_level >= 7) {
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get_cpuid(®s, 7);
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if (regs.ebx & (1 << 5)) cpu_flags |= cpu_avx2;
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}
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get_cpuid(®s, 0x80000000);
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max_ext_level = regs.eax;
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if (max_ext_level >= 0x80000001) {
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get_cpuid(®s, 0x80000001);
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if (regs.ecx & (1 << 11)) cpu_flags |= cpu_xop;
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}
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}
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#if defined(SCRYPT_TEST_SPEED)
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cpu_flags &= cpu_detect_mask;
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#endif
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return cpu_flags;
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}
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#if defined(SCRYPT_TEST_SPEED)
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static const char *
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get_top_cpuflag_desc(size_t flag) {
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if (flag & cpu_avx2) return "AVX2";
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else if (flag & cpu_xop) return "XOP";
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else if (flag & cpu_avx) return "AVX";
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else if (flag & cpu_sse4_2) return "SSE4.2";
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else if (flag & cpu_sse4_1) return "SSE4.1";
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else if (flag & cpu_ssse3) return "SSSE3";
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else if (flag & cpu_sse2) return "SSE2";
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else if (flag & cpu_sse) return "SSE";
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else if (flag & cpu_mmx) return "MMX";
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else return "Basic";
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}
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#endif
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/* enable the highest system-wide option */
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#if defined(SCRYPT_CHOOSE_COMPILETIME)
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#if !defined(__AVX2__)
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#undef X86_64ASM_AVX2
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#undef X86ASM_AVX2
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#undef X86_INTRINSIC_AVX2
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#endif
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#if !defined(__XOP__)
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#undef X86_64ASM_XOP
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#undef X86ASM_XOP
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#undef X86_INTRINSIC_XOP
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#endif
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#if !defined(__AVX__)
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#undef X86_64ASM_AVX
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#undef X86ASM_AVX
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#undef X86_INTRINSIC_AVX
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#endif
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#if !defined(__SSSE3__)
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#undef X86_64ASM_SSSE3
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#undef X86ASM_SSSE3
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#undef X86_INTRINSIC_SSSE3
|
|
#endif
|
|
#if !defined(__SSE2__)
|
|
#undef X86_64ASM_SSE2
|
|
#undef X86ASM_SSE2
|
|
#undef X86_INTRINSIC_SSE2
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* defined(CPU_X86) || defined(CPU_X86_64) */ |